Chisel-Verilog Aligner
Formally verified signal mapping from optimized Verilog back to Chisel source (undergraduate thesis)
Advisor: Prof. Nathaniel Bleier, University of Michigan · 2026/01 – 2026/05
- Developed a formally verified Chisel-Verilog aligner that leverages Yosys and FIRRTL to map optimized Verilog signals back to the original Chisel source with signal-level accuracy.
- Resolved traceability bottlenecks in agile hardware design, outperforming ML-driven methods and enabling downstream applications such as automated HDL debugging, semi-formal verification, and AI-driven testbench generation.