Out-of-Order RISC-V Processor
EECS 470 superscalar R10K-style core, ranked top 2 in the course
EECS 470, University of Michigan · 2025/02 – 2025/05
- Designed the RTL of an out-of-order RV32IM processor based on the MIPS R10K microarchitecture.
- Implemented N-way superscalar execution, early branch resolution, early tag broadcast, prefetching, non-blocking associative caches, a load/store queue with forwarding, and a cycle-accurate simulator.
- Integrated TAGE, perceptron, and CNN-based branch predictors with a branch target buffer and return address stack.
- Achieved an average CPI of 1.68 at a 10 ns clock period; the final design ranked top 2 in the course.